Challenges in the Design of High-Speed Clock and Data Recovery Circuits
نویسنده
چکیده
This article describes the challenges in the design of monolithic clock and data recovery circuits used in high-speed transceivers. Following an overview of general issues, the task of phase detection for random data is addressed. Next, Hogge, Alexander, and half-rate phase detectors are introduced and their trade-offs outlined. Finally, a number of clock and data recovery architectures are presented.
منابع مشابه
A High-Speed Dual-Bit Parallel Adder based on Carbon Nanotube FET technology for use in arithmetic units
In this paper, a Dual-Bit Parallel Adder (DBPA) based on minority function using Carbon-Nanotube Field-Effect Transistor (CNFET) is proposed. The possibility of having several threshold voltage (Vt) levels by CNFETs leading to wide use of them in designing of digital circuits. The main goal of designing proposed DBPA is to reduce critical path delay in adder circuits. The proposed design positi...
متن کاملA new low power high reliability flip-flop robust against process variations
Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In ...
متن کاملModeling of Jitter Characteristics for the Second Order Bang-Bang CDR
Bang-Bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by formulating the time domain waveforms. As a re...
متن کاملHigh Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
متن کاملDesign of a 6.25 Gbps Backplane SerDes with TOP-down Design Methodology
SerDes design exceeding 6.25 Gbps for existing backplanes has to overcome significant signal integrity challenges on channel attenuation, cross talk, and multiple reflections. Adaptive decision feedback equalization becomes a requirement to overcome these challenges. The non-ideality from silicon implementation is not negligible for bit error rate degradation. This paper presents a 6.25 Gbps ba...
متن کامل